Remote Jobs at Brickred Systems

Join our client’s Silicon Team to drive innovation in consumer electronic devices and cloud computing. We’re seeking a Mask Layout Design Engineer passionate about IC Layout design for high-speed CMOS Interface and SERDES technologies. Key Responsibilities... • Execute IC layout for high-performance CMOS Interface D2D and SERDES in 2nm and 3nm CMOS process nodes. • Utilize Cadence Virtuoso for analog IP layouts such as PLLs, ADCs, RX, TX, OTAs, LDO, and Clock Distribution. • Conduct layout design reviews, floor-planning, LVS, DRC, and DFM. Requirements: • 0-2 years of experience in high-performance analog layout; FINFET CMOS process preferred. • Strong knowledge of EDA tools (Cadence, Mentor, Synopsys). • Familiarity with analog blocks layout (e.g., VCOs, chargepumps, PLLs, ADCs). • Skills in floor planning, block-level routing, and high-speed IO design. • Proficiency in advanced layout techniques like matching, symmetrical layout, and signal shielding. Top Skill ...

Join our client’s Silicon Team to drive innovation in consumer electronic devices and cloud computing. We’re seeking a Mask Layout Design Engineer passionate about IC Layout design for high-speed CMOS Interface and SERDES technologies. Key Responsibilities... • Execute IC layout for high-performance CMOS Interface D2D and SERDES in 2nm and 3nm CMOS process nodes. • Utilize Cadence Virtuoso for analog IP layouts such as PLLs, ADCs, RX, TX, OTAs, LDO, and Clock Distribution. • Conduct layout design reviews, floor-planning, LVS, DRC, and DFM. Requirements: • 0-2 years of experience in high-performance analog layout; FINFET CMOS process preferred. • Strong knowledge of EDA tools (Cadence, Mentor, Synopsys). • Familiarity with analog blocks layout (e.g., VCOs, chargepumps, PLLs, ADCs). • Skills in floor planning, block-level routing, and high-speed IO design. • Proficiency in advanced layout techniques like matching, symmetrical layout, and signal shielding. Top Skill ...

Join our client’s Silicon Team to drive innovation in consumer electronic devices and cloud computing. We’re seeking a Mask Layout Design Engineer passionate about IC Layout design for high-speed CMOS Interface and SERDES technologies. Key Responsibilities... • Execute IC layout for high-performance CMOS Interface D2D and SERDES in 2nm and 3nm CMOS process nodes. • Utilize Cadence Virtuoso for analog IP layouts such as PLLs, ADCs, RX, TX, OTAs, LDO, and Clock Distribution. • Conduct layout design reviews, floor-planning, LVS, DRC, and DFM. Requirements: • 0-2 years of experience in high-performance analog layout; FINFET CMOS process preferred. • Strong knowledge of EDA tools (Cadence, Mentor, Synopsys). • Familiarity with analog blocks layout (e.g., VCOs, chargepumps, PLLs, ADCs). • Skills in floor planning, block-level routing, and high-speed IO design. • Proficiency in advanced layout techniques like matching, symmetrical layout, and signal shielding. Top Skill ...

Join our client’s Silicon Team to drive innovation in consumer electronic devices and cloud computing. We’re seeking a Mask Layout Design Engineer passionate about IC Layout design for high-speed CMOS Interface and SERDES technologies. Key Responsibilities... • Execute IC layout for high-performance CMOS Interface D2D and SERDES in 2nm and 3nm CMOS process nodes. • Utilize Cadence Virtuoso for analog IP layouts such as PLLs, ADCs, RX, TX, OTAs, LDO, and Clock Distribution. • Conduct layout design reviews, floor-planning, LVS, DRC, and DFM. Requirements: • 0-2 years of experience in high-performance analog layout; FINFET CMOS process preferred. • Strong knowledge of EDA tools (Cadence, Mentor, Synopsys). • Familiarity with analog blocks layout (e.g., VCOs, chargepumps, PLLs, ADCs). • Skills in floor planning, block-level routing, and high-speed IO design. • Proficiency in advanced layout techniques like matching, symmetrical layout, and signal shielding. Top Skill ...